The present invention relates generally to isolation structures for integrated circuits, and more particularly to shallow trench isolation methods and structures.
Integrated circuit devices typically include a number of active devices, such as transistors, that are separated from one another by isolation structures. Isolation structures help to ensure that active devices can be individually controlled by preventing current flow between adjacent devices. Without sufficient isolation, leakage paths can occur between active devices, leading to a number of undesirable effects. Such undesirable effects can include increased power dissipation, increased susceptibility to latch-up, unstable logic states, and decreased noise margins.
Integrated circuits are often manufactured with generational decreases in device sizes. That is, while an initial manufacturing process may be capable of fabricating active devices with an initial minimum feature size, as processing technology progresses, the minimum size continues to decrease. As just one example, a process may initially be capable of fabricating insulated gate transistors having a minimum gate length of 0.5 microns (xcexcm). With improvements in process technology, smaller gate lengths are possible. For example, gate lengths of 0.25 or 0.21 xcexcm can be achieved.
Decreases in minimum active device size can result in integrated circuit devices designs being subjected to generational xe2x80x9cshrinks.xe2x80x9d Generational shrinks involve using an existing basic design, but then shrinking the structures within the design according to process improvements. Each shrink can result in an integrated circuit having an overall smaller physical size. Smaller integrated circuit sizes allow more integrated circuits to be fit on a wafer, which can result in a more cost-effective production.
While process improvements can allow for the shrinking of certain device structures, other device structures are not always capable of being reduced in size. In particular, as device features (xe2x80x9cgeometriesxe2x80x9d) continue to shrink, it can be increasingly more difficult to achieve a corresponding shrink in an isolation structure.
One type of isolation structure that is commonly employed in integrated circuits that are fabricated on a silicon substrate, is the local oxidation of silicon xe2x80x9cLOCOS.xe2x80x9d LOCOS involves placing a barrier layer (silicon nitride for example) over the semiconductor substrate. Openings are then formed in the barrier layer. The exposed portion of the silicon substrate is oxidized to create a silicon dioxide xe2x80x9cfield oxide.xe2x80x9d The field oxide has tapered edges (xe2x80x9cbird""s beakxe2x80x9d) that extend under edges of the barrier layer, encroaching into the active portions of the substrate. The encroachment can result in larger isolation structures in the lateral direction (parallel to the semiconductor substrate). For this reason, LOCOS-type isolation can be undesirable.
In addition to extending in a lateral direction, LOCOS structures can extend in the vertical direction, above the substrate. Consequently, LOCOS structures can add to the topography of semiconductor device. Additional topography can be undesirable as it can complicate subsequent patterning step. Furthermore, because LOCOS is essentially xe2x80x9cgrownxe2x80x9d in the oxide, smaller lateral dimensions correspond to smaller vertical dimensions. Accordingly, while LOCOS structures having smaller lateral features can be formed, such structures will have very small vertical depth. LOCOS structures having too small a vertical depth, provide less reliable isolation, and are more susceptible to functioning as a parasitic transistor, in the event a conductive line is situated over the LOCOS structure.
An alternative to LOCOS, and LOCOS-type isolation is shallow trench isolation (STI). Conventional STI approaches involve etching a trench into a substrate, and then filling the trench with an isolation material. In this way, lateral and vertical dimensions of an isolation structure can be established by an etch step. While conventional STI approaches can result in smaller isolation structures, such approaches can have drawbacks. To better understand these drawbacks, a conventional STI method and associated structure will now be described.
Referring now to FIG. 1, a flow diagram is set forth that describes a conventional STI method. The conventional STI method is used to form an isolation structure in a silicon substrate. The method set forth in the flow diagram is designated by the general reference character 100 and is shown to include a number of steps, each of which involves one or more fabrication steps. FIGS. 2A-2G are side cross-sectional views illustrating the formation of a conventional STI structure made according to the method set forth in FIG. 1.
The flow diagram 100 is shown to include a xe2x80x9cThin Oxide/Nitride Depositionxe2x80x9d step 102. Step 102 involves forming a thin silicon dioxide (xe2x80x9coxidexe2x80x9d) layer on a silicon substrate, and then depositing a silicon nitride (xe2x80x9cnitridexe2x80x9d) layer over the oxide layer. FIG. 2A sets forth a side cross-sectional view of a conventional STI structure following step 102. The STI structure is designated by the general reference character 200, and is shown to include a silicon substrate 202. A relatively thin layer of oxide 204 has been formed on the silicon substrate 202. Deposited over the relatively thin layer of oxide 204 is a layer of nitride 206.
Following step 102, the STI flow diagram 100 continues with a xe2x80x9cPhoto Patternxe2x80x9d step 104. Step 104 involves forming an etch mask over the nitride layer using photolithographic steps. A side cross-sectional view of the STI structure 200 following step 104 is set forth in FIG. 2B. The resulting etch mask is shown to include developed photoresist (xe2x80x9cresistxe2x80x9d) 208 formed over an anti-reflective coating (ARC) 210. The ARC 210 can reduce corner reflections that result in unwanted rounding of pattern corners or other undesirable results. An etch mask opening 212 is formed within the resist 208 and the ARC 210, resulting in a portion of the nitride layer 206 being exposed.
Following step 104, the conventional STI flow diagram 100 continues with a xe2x80x9cNitride Etch (stop on oxide)xe2x80x9d step 106. Step 106 involves applying a silicon nitride etch that results in the removal of that portion of the nitride layer that is exposed by the resist pattern 208. A side cross-sectional view of the STI structure 200 following step 106 is set forth in FIG. 2C. The opening 212 following the silicon nitride etch is shown to extend through the nitride layer 206 to the relatively thin oxide layer 204. Also set forth in FIG. 2C, by dashed lines, are residual nitride xe2x80x9cparticlesxe2x80x9d 214 within the etch mask opening 212. Such particles can arise despite concerted efforts to have as clean a process as possible.
Following step 104, the STI flow diagram 100 continues with a xe2x80x9cSi Etch (Form the trench in Si substrate)xe2x80x9d step 108. Step 108 involves applying a silicon etch. FIG. 2D sets forth a side cross-sectional view of the STI structure 200 following step 108. The silicon etch has formed a silicon trench 216 below the etch mask opening 212. Also set forth in FIG. 2D, by dashed lines, are xe2x80x9cmicro-maskingxe2x80x9d defects 218 arising from the particles 214 formed in the previous nitride etch step. The nitride particles 214 function essentially as etch masks during the silicon etch, and can result in undesirable uneven topography in the bottom of a silicon trench, including silicon xe2x80x9cpillars.xe2x80x9d
Following the silicon etch (step 108), a xe2x80x9cLiner Oxidationxe2x80x9d step 110 is performed. Liner oxidation involves forming a relatively thin layer of oxide on the exposed surfaces of a trench in the silicon substrate. FIG. 2E sets forth a side cross-sectional view of the STI structure 200 following step 110. The resulting thin oxide layer 220 can be considered a xe2x80x9cliner oxide,xe2x80x9d as it lines the vertical and horizontal surfaces within the trench 216. As shown by dashed lines in FIG. 2E, the liner oxide 220 can be formed on micro-masking defects 218.
Following the creation of the liner oxide 220, the flow chart 100 continues with an xe2x80x9cHDP Gap Fill/Dens,xe2x80x9d step 112. Step 112 involves depositing an oxide layer with a high density plasma (HDP) to fill the gaps (trenches) created by the silicon etch step 108. Following the oxide deposition, the deposited oxide is then densified (DENS). FIG. 2F sets forth a side cross-sectional view of the STI structure 200 following step 112. An HDP oxide is designated by the reference character 222 and is shown to extend over, and into the trench 216.
The last step set forth in the flow chart 200 is a xe2x80x9cCMP/Nitride Stripxe2x80x9d step 114. Step 114 involves chemical mechanical polishing (CMP) and the removal of nitride situated over the silicon substrate. FIG. 2G sets forth a side cross-sectional view of the STI structure 200 following step 114. The STI structure 200 includes a trench isolation 224 formed by the liner oxide and remaining HDP oxide. In addition, due to the CMP process, the trench isolation 224 includes a portion (a xe2x80x9cstudxe2x80x9d) 226 that extends above the substrate 202 surface. The previous trench etching step in combination with the CMP operation results in relatively sharp corners 228a and 228b formed at the junction of the vertical walls of the trench and the horizontal substrate surface. Also identified in FIG. 2G are corner oxide portions 230a and 230b. The corner oxide portions (230a and 230b) are those portions of the trench isolation 224 that are adjacent to the relatively sharp corners (228a and 228b).
As noted above, the conventional STI structure 200 set forth in FIG. 2G can be susceptible to a number of drawbacks. In particular, the relatively sharp corners (228a and 228b) can result in increased stress on the corners. Increased stress can result in increased numbers of dislocations in the silicon crystal lattice structure making up the relatively sharp corners (228a and 228b). Increased dislocations can result in increased leakage current. The relatively sharp corners will also produced increased electric fields. Increased electrical fields can produce more leakage current and/or decrease the overall reliability of an integrated circuit.
The thickness of the corner oxide portions (230a and 230b) can also affect an integrated circuit. Thin corner oxide portions (228a and 228b) can result in less insulation for the corners from subsequently deposited conductive layers. Less insulation at the relatively sharp corners (228a and 228b) can further increase leakage and/or reduce reliability.
Increased leakage current will result in increased power consumption and increased stand-by current. In the event metal-oxide-semiconductor (MOS) transistors are separated by conventional STI structures 200, increased leakage current can manifest itself as sub-threshold current. Such sub-threshold current will often introduce a xe2x80x9chumpxe2x80x9d in the sub-threshold current response of a MOS transistor.
The conventional STI approach described in FIG. 1 and FIGS. 2A-2G, can also produce micro-masking defects, such as those illustrated by the reference character 218. Such defects can result in inadequate isolation and/or adversely affect the reliability of the resulting integrated circuit.
It is also noted that the resulting conventional STI structure 226 produces a trench isolation 224 having a stud 226. The stud 226 extends above the surface of the substrate 202. The stud 226 can introduce topographical variations into subsequent deposited layers. Such variations (e.g., uneven surfaces) can adversely affect patterning of subsequently deposited layers. As just one example, a polysilicon layer can be deposited after the formation of the STI structures. The polysilicon layer will then have to be patterned to form gates for MOS transistors. The topography introduced by overly large trench isolation studs 226 can adversely effect the patterning of gate structures. Consequently, resulting gate structures can be too wide or too narrow.
Accordingly, while a conventional STI approach can produce isolation structures having smaller geometries, such structures can have drawbacks.
To further understand the various embodiments that will be described, a further discussion of general semiconductor device manufacturing, for both discrete and integrated circuits, will be discussed. Most semiconductor device manufacturing processes involve a series of steps that deposit and/or pattern multiple layers. Often such steps are restrictive, in that the steps can only be performed in a certain way, or by a certain machine. As just one example, etching steps for certain materials can be performed by a xe2x80x9cwetxe2x80x9d chemical etch, or by a xe2x80x9cdryxe2x80x9d plasma etch. In the event the etching step involved in creating a semiconductor device can be performed by either a dry etch or a wet etch, the manufacture of the semiconductor device is more flexible. Consequently, the semiconductor device can be more amenable to being manufactured at different facilities, or less susceptible to slow production times, by being overly dependent upon a particular manufacturing step.
Another feature of a semiconductor device is process integration flexibility. When a semiconductor memory device is manufactured, the structure produced by one manufacturing step can be adversely affected by subsequent process steps. This can result in a process in which step must be very subject to tight controls (have narrow process margins). One such structure in the conventional STI structure is the corner oxide portions (230a and 230b) set forth in FIG. 2G. Once a conventional STI structure is formed, the corner oxide portions (230a and 230b) are susceptible to thing by any subsequent etching steps. Accordingly, subsequent etching steps must be tightly controlled to prevent over-etching of the corner oxide portions (230a and 230b). In this way, the corner protection afforded by conventional STI approaches can result in reduced process margins.
Yet another feature of semiconductor device manufacturing processes is the number of discrete manufacturing steps required to form a semiconductor device structure. Reducing the number of steps in a manufacturing process can increase the number of devices that can be produced in a given time period (throughput) and reduce the overall cost involved in manufacturing each device. A similar manufacturing feature that should also be considered is manufacturing simplicity. Manufacturing simplicity can include performing multiple manufacturing steps with the same piece of equipment. Such manufacturing simplicity can also increase throughput and reduce cost.
One way to reduce manufacturing steps and/or simplify manufacturing, while at the same time providing small geometry structures, is to use self-aligned steps. Self-aligned steps typically involve using one mask structure for multiple process steps. For example, a self-aligned contact will use one mask to both define a contact opening and form a substrate contact in the opening.
In light of the advantages of STI structures in reducing the size of an integrated circuit, it would be desirable to provide some way of forming an STI structure that differs from conventional approaches. It would also be desirable to provide such an alternate STI method that does not include one or more of the drawbacks inherent in many conventional STI approaches. It would also be desirable to arrive at an STI approach that has process flexibility, or increased process margins, or reduced manufacturing steps, or increased manufacturing simplicity.
According to the disclosed embodiments, a number of trench isolation methods are disclosed. According to one aspect of the disclosed embodiments, a trench isolation method includes forming a barrier mask over a substrate. The barrier mask has an opening that exposes a portion of the substrate. A substrate consuming layer is formed over the exposed portion of the substrate forming rounded corners in the substrate. The substrate consuming layer is removed, resulting in a gouge within the substrate surface that includes the rounded corners. A trench is formed within the gouge so that the trench edges include the rounded edges formed by the substrate consuming layer.
According to another aspect of the disclosed embodiments, a trench isolation method includes forming an etch mask layer over a substrate. The etch mask layer is patterned with an etch step to form an opening in the etch mask. A substrate consuming layer is formed on the portion of the substrate exposed by the etch mask. The substrate consuming layer is then subsequently removed. The formation and removal of the substrate consuming layer can remove defect introduced by the etch step used to pattern the etch mask.
According to another aspect of the disclosed embodiments, a trench isolation method includes forming a barrier mask over a substrate. The barrier mask has an opening that exposes a portion of the substrate. A substrate consuming layer is formed over the exposed portion of the substrate. The barrier mask limits the lateral extents of the substrate consuming layer, and results in portions of the substrate consuming layer (xe2x80x9cencroaching portionsxe2x80x9d) extending under the barrier mask. Portions of the substrate consuming layer are removed with a substantially anisotropic etch, resulting in the removal of the majority of the substrate consuming layer, but the preservation of the encroaching portions. A trench is then etched in the substrate using the barrier mask as an etch mask. The resulting trench has corners that are protected by the encroaching portions.
According to another aspect of the embodiments a shallow trench isolation structure includes a trench formed in a silicon substrate. The trench has sides that are connected to the substrate surface by rounded edges. An encroaching portion, formed from thermal silicon dioxide, is formed over the rounded edges. The remainder of the trench is filled with a trench isolation material.
An advantage of at least one of the disclosed embodiments is that it provides a trench isolation structure having a trench with rounded corners.
Another advantage of at least one of the disclosed embodiments is that it provides a trench isolation method that can remove particles or other defects that can adversely affect a trench etch step.
Another advantage of at least one of the disclosed embodiments is that it provides a trench isolation structure having a trench with additional insulation protection over the trench edges.
Another advantage of at least one of the disclosed embodiments is that it can provide a trench isolation structure having less topography than some conventional trench isolation approaches.
Another advantage of at least one of the disclosed embodiments is that it can provide a trench isolation method that is self-aligned.